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PD - 95850 DIGITAL AUDIO MOSFET Features Advanced Process Technology l Key Parameters Optimized for Class-D Audio Amplifier Applications l Low RDSON for Improved Efficiency l Low Qg and Qsw for Better THD and Improved Efficiency l Low Qrr for Better THD and Lower EMI l 175C Operating Junction Temperature for Ruggedness l Repetitive Avalanche Capability for Robustness and Reliability l Multiple Package Options l IRLR9343 IRLU9343 IRLU9343-701 Key Parameters -55 93 150 31 175 V m: m: nC C VDS RDS(ON) typ. @ VGS = -10V RDS(ON) typ. @ VGS = -4.5V Qg typ. TJ max D G S I-Pak IRLU9343 I-Pak Leadform 701 IRLU9343-701 Refer to page 10 for package outline D-Pak IRLR9343 Description This Digital Audio HEXFET(R) is specifically designed for Class-D audio amplifier applications. This MosFET utilizes the latest processing techniques to achieve low on-resistance per silicon area. Furthermore, Gate charge, body-diode reverse recovery and internal Gate resistance are optimized to improve key Class-D audio amplifier performance factors such as efficiency, THD and EMI. Additional features of this MosFET are 175C operating junction temperature and repetitive avalanche capability. These features combine to make this MosFET a highly efficient, robust and reliable device for Class-D audio amplifier applications. Absolute Maximum Ratings Parameter VDS VGS ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C PD @TC = 100C TJ TSTG Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current, VGS @ -10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current c Power Dissipation Power Dissipation Linear Derating Factor Operating Junction and Storage Temperature Range Clamping Pressure h --- N Max. -55 20 -20 -14 -60 79 39 0.53 -40 to + 175 Units V A W W/C C Thermal Resistance Parameter RJC RJA RJA Junction-to-Case g Junction-to-Ambient (PCB Mounted) gj Junction-to-Ambient (free air) g Typ. --- --- --- Max. 1.9 50 110 Units C/W Notes through are on page 10 www.irf.com 1 4/1/04 IRLR/U9343 & IRLU9343-701 Electrical Characteristics @ TJ = 25C (unless otherwise specified) Parameter BVDSS VDSS/TJ RDS(on) VGS(th) VGS(th)/TJ IDSS IGSS gfs Qg Qgs Qgd Qgodr td(on) tr td(off) tf Ciss Coss Crss Coss LD LS Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Gate Threshold Voltage Coefficient Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain Charge Gate Charge Overdrive Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Effective Output Capacitance Internal Drain Inductance Internal Source Inductance Min. -55 --- --- --- -1.0 --- --- --- --- --- 5.3 --- --- --- --- --- --- --- --- --- --- --- --- --- --- Typ. Max. Units --- -52 93 150 --- -3.7 --- --- --- --- --- 31 7.1 8.5 15 9.5 24 21 9.5 660 160 72 280 4.5 7.5 --- --- 105 170 --- --- -2.0 -25 -100 100 --- 47 --- --- --- --- --- --- --- --- --- --- --- --- nH --- pF VGS = 0V VDS = -50V ns S nA V Conditions VGS = 0V, ID = -250A mV/C Reference to 25C, ID = -1mA m VGS = -10V, ID = -3.4A e VGS = -4.5V, ID = -2.7A e V mV/C A VDS = -55V, VGS = 0V VDS = -55V, VGS = 0V, TJ = 125C VGS = -20V VGS = 20V VDS = -25V, ID = -14A VDS = -44V VGS = -10V ID = -14A See Fig. 6 and 19 VDD = -28V, VGS = -10V e ID = -14A RG = 2.5 VDS = VGS, ID = -250A = 1.0MHz, Between lead, 6mm (0.25in.) from package See Fig.5 VGS = 0V, VDS = 0V to -44V and center of die contact f Avalanche Characteristics Parameter Typ. Max. Units mJ A mJ EAS IAR EAR Single Pulse Avalanche Energyd Avalanche Current i Repetitive Avalanche Energy i --- 120 See Fig. 14, 15, 17a, 17b Diode Characteristics Parameter IS @ TC = 25C Continuous Source Current ISM VSD trr Qrr (Body Diode) Pulsed Source Current (Body Diode) c Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Min. --- --- --- --- --- Typ. Max. Units --- --- --- 57 120 -20 A -60 -1.2 86 180 V ns nC Conditions MOSFET symbol showing the integral reverse G D S p-n junction diode. TJ = 25C, IS = -14A, VGS = 0V e TJ = 25C, IF = -14A di/dt = 100A/s e 2 www.irf.com IRLR/U9343 & IRLU9343-701 100 TOP VGS -15V -12V -10V -8.0V -5.5V -4.5V -3.0V -2.5V 100 TOP VGS -15V -12V -10V -8.0V -5.5V -4.5V -3.0V -2.5V -I D, Drain-to-Source Current (A) -I D, Drain-to-Source Current (A) 10 BOTTOM 10 BOTTOM 1 1 -2.5V 60s PULSE WIDTH Tj = 175C -2.5V 60s PULSE WIDTH Tj = 25C 10 100 0.1 0.1 1 0.1 0.1 1 10 100 -VDS, Drain-to-Source Voltage (V) -VDS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics 100.0 Fig 2. Typical Output Characteristics 2.0 RDS(on) , Drain-to-Source On Resistance (Normalized) -I D, Drain-to-Source Current () T J = 25C T J = 175C 10.0 ID = -14A VGS = -10V 1.5 1.0 1.0 VDS = -25V 60s PULSE WIDTH 0.1 0.0 5.0 10.0 15.0 0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 -V GS, Gate-to-Source Voltage (V) T J , Junction Temperature (C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature 20 -VGS, Gate-to-Source Voltage (V) 10000 VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd ID= -14A 16 C, Capacitance (pF) VDS= -44V VDS= -28V VDS= -11V 1000 Ciss Coss 100 12 8 Crss 4 FOR TEST CIRCUIT SEE FIGURE 19 10 1 10 100 0 0 10 20 30 40 50 QG Total Gate Charge (nC) -V DS, Drain-to-Source Voltage (V) Fig 5. Typical Capacitance vs.Drain-to-Source Voltage Fig 6. Typical Gate Charge vs.Gate-to-Source Voltage www.irf.com 3 IRLR/U9343 & IRLU9343-701 100.0 1000 -I SD, Reverse Drain Current (A) T J = 175C 10.0 -I D, Drain-to-Source Current (A) OPERATION IN THIS AREA LIMITED BY R DS(on) 100 1.0 T J = 25C 100sec 10 VGS = 0V 0.1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 1 1 Tc = 25C Tj = 175C Single Pulse 10 1msec 10msec 100 1000 -V SD, Source-to-Drain Voltage (V) -VDS , Drain-toSource Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage 20 2.5 Fig 8. Maximum Safe Operating Area 16 -VGS(th) Gate threshold Voltage (V) -I D , Drain Current (A) 2.0 12 ID = -250A 1.5 8 4 0 25 50 75 100 125 150 175 1.0 -75 -50 -25 0 25 50 75 100 125 150 175 T J , Junction Temperature (C) T J , Temperature ( C ) Fig 9. Maximum Drain Current vs. Case Temperature 10 Fig 10. Threshold Voltage vs. Temperature Thermal Response ( Z thJC ) 1 D = 0.50 0.20 0.10 0.1 0.05 0.02 0.01 J R1 R1 J 1 2 R2 R2 C 2 Ri (C/W) 1.162 0.7370 i (sec) 0.000512 0.002157 1 0.01 Ci= i/Ri Ci i/Ri SINGLE PULSE ( THERMAL RESPONSE ) 0.001 1E-006 1E-005 0.0001 0.001 Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.01 0.1 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case 4 www.irf.com IRLR/U9343 & IRLU9343-701 RDS(on), Drain-to -Source On Resistance ( m) EAS, Single Pulse Avalanche Energy (mJ) 600 500 ID = -14A 500 400 ID -4.0A -5.5A BOTTOM -14A TOP 400 300 300 200 200 T J = 125C 100 100 0 4.0 6.0 T J = 25C 8.0 10.0 0 25 50 75 100 125 150 175 -V GS, Gate-to-Source Voltage (V) Starting T J, Junction Temperature (C) Fig 12. On-Resistance Vs. Gate Voltage 1000 Fig 13. Maximum Avalanche Energy Vs. Drain Current Duty Cycle = Single Pulse -Avalanche Current (A) 100 0.01 10 Allowed avalanche Current vs avalanche pulsewidth, tav assuming Tj = 25C due to avalanche losses. Note: In no case should Tj be allowed to exceed Tjmax 0.05 0.10 1 0.1 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 tav (sec) Fig 14. Typical Avalanche Current Vs.Pulsewidth 140 120 EAR , Avalanche Energy (mJ) TOP Single Pulse BOTTOM 1% Duty Cycle ID = -14A 100 80 60 40 20 0 25 50 75 100 125 150 175 Starting T J , Junction Temperature (C) Fig 15. Maximum Avalanche Energy Vs. Temperature Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 17a, 17b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav *f ZthJC(D, tav) = Transient thermal resistance, see figure 11) PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav www.irf.com 5 IRLR/U9343 & IRLU9343-701 D.U.T Driver Gate Drive + P.W. Period D= P.W. Period VGS=10V + Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer * D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt - - + RG * * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test VDD VDD + - Re-Applied Voltage Body Diode Forward Drop Inductor Inductor Curent Current Ripple 5% ISD * Reverse Polarity of D.U.T for P-Channel * VGS = 5V for Logic Level Devices Fig 16. Peak Diode Recovery dv/dt Test Circuit for P-Channel HEXFET(R) Power MOSFETs VDS L VDS RG -VGS -20V RD D.U.T IAS VDD A DRIVER VGS RG -10V D.U.T. + 15V Pulse Width 1 s Duty Factor 0.1 % Fig 17a. Unclamped Inductive Test Circuit I AS Fig 18a. Switching Time Test Circuit td(on) tr t d(off) tf VGS 10% tp V(BR)DSS 90% VDS Fig 17b. Unclamped Inductive Waveforms Fig 18b. Switching Time Waveforms Id Vds Vgs L DUT 0 VCC Vgs(th) 1K Qgs1 Qgs2 Qgd Qgodr Fig 19a. Gate Charge Test Circuit Fig 19b Gate Charge Waveform 6 - tp 0.01 VDD www.irf.com IRLR/U9343 & IRLU9343-701 D-Pak (TO-252AA) Package Outline Dimensions are shown in millimeters (inches) 6.73 (.265) 6.35 (.250) -A5.46 (.215) 5.21 (.205) 4 1.27 (.050) 0.88 (.035) 2.38 (.094) 2.19 (.086) 1.14 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.018) 6.45 (.245) 5.68 (.224) 6.22 (.245) 5.97 (.235) 1.02 (.040) 1.64 (.025) 1 2 3 0.51 (.020) MIN. 10.42 (.410) 9.40 (.370) LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN -B1.52 (.060) 1.15 (.045) 1.14 (.045) 2X 0.76 (.030) 2.28 (.090) 4.57 (.180) 0.89 (.035) 3X 0.64 (.025) 0.25 (.010) M AMB NOTES: 0.58 (.023) 0.46 (.018) 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX. +0.16 (.006). D-Pak (TO-252AA) Part Marking Information Notes : This part marking information applies to devices produced before 02/26/2001 EXAMPLE: T HIS IS AN IRFR120 WIT H AS SEMBLY LOT CODE 9U1P INT ERNAT IONAL RECT IFIER LOGO ASS EMBLY LOT CODE IRFU120 9U 016 1P DAT E CODE YEAR = 0 WEEK = 16 Notes : T his part marking information applies to devices produced after 02/26/2001 EXAMPLE: T HIS IS AN IRFR120 WIT H AS SEMBLY LOT CODE 1234 AS SEMBLED ON WW 16, 1999 IN T HE AS S EMBLY LINE "A" PART NUMBER IRFU120 12 916A 34 INT ERNAT IONAL RECT IFIER LOGO ASS EMBLY LOT CODE DAT E CODE YEAR 9 = 1999 WEEK 16 LINE A www.irf.com 7 IRLR/U9343 & IRLU9343-701 I-Pak (TO-251AA) Package Outline Dimensions are shown in millimeters (inches) 6.73 (.265) 6.35 (.250) -A5.46 (.215) 5.21 (.205) 4 6.45 (.245) 5.68 (.224) 1.52 (.060) 1.15 (.045) 1 -B2.28 (.090) 1.91 (.075) 9.65 (.380) 8.89 (.350) 2 3 NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX. +0.16 (.006). 1.14 (.045) 0.76 (.030) 6.22 (.245) 5.97 (.235) 1.27 (.050) 0.88 (.035) 2.38 (.094) 2.19 (.086) 0.58 (.023) 0.46 (.018) LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN 3X 3X 0.89 (.035) 0.64 (.025) M AMB 1.14 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.018) 2.28 (.090) 2X 0.25 (.010) I-Pak (TO-251AA) Part Marking Information Notes : T his part marking information applies to devices produced before 02/26/2001 EXAMPLE: T HIS IS AN IRFR120 WIT H AS S EMBLY LOT CODE 9U1P INT ERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE DAT E CODE YEAR = 0 WEEK = 16 IRFU120 016 9U 1P Notes : T his part marking information applies to devices produced after 02/26/2001 EXAMPLE: T HIS IS AN IRFR120 WIT H AS S EMBLY LOT CODE 5678 AS SEMBLED ON WW 19, 1999 IN T HE AS S EMBLY LINE "A" INT ERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE PART NUMBER IRFU120 919A 56 78 DAT E CODE YEAR 9 = 1999 WEEK 19 LINE A 8 www.irf.com IRLR/U9343 & IRLU9343-701 D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR TRL 16.3 ( .641 ) 15.7 ( .619 ) 16.3 ( .641 ) 15.7 ( .619 ) 12.1 ( .476 ) 11.9 ( .469 ) FEED DIRECTION 8.1 ( .318 ) 7.9 ( .312 ) FEED DIRECTION NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541. 13 INCH 16 mm NOTES : 1. OUTLINE CONFORMS TO EIA-481. www.irf.com 9 IRLR/U9343 & IRLU9343-701 I-Pak Leadform Option 701 Package Outline Dimensions are shown in millimeters (inches) Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting TJ = 25C, L = 1.24mH, RG = 25, IAS = -14A. Pulse width 400s; duty cycle 2%. This only applies for I-Pak, LS of D-Pak is measured between lead and center of die contact R is measured at TJ of approximately 90C. Contact factory for mounting information Limited by Tjmax. See Figs. 14, 15, 17a, 17b for repetitive avalanche information When D-Pak mounted on 1" square PCB (FR-4 or G-10 Material) . For recommended footprint and soldering techniques refer to application note #AN-994 Refer to D-Pak package for Part Marking, Tape and Reel information. Data and specifications subject to change without notice. This product has been designed for the Industrial market. Qualification Standards can be found on IR's Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.4/04 10 www.irf.com |
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